GDDAQ

Welcome to GDDAQ’s guides.

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Introduction

• Introduction
  • Version
  • About
  • File contents
  • Update plan
  • License

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Install

• Installation of ROOT GUI Software
  • The steps for Installation
  • Instruction for use
  • Common installation errors
    • Ubuntu 22.04
    • Ubuntu 20.04
    • Ubuntu 18.04
    • CentOS8
    • CentOS7
  • 9054 driver loading error
  • TeamViewer
• MYSQL
  • MYSQL installation steps
    • CentOS 7
    • Ubuntu 18.04LTS
  • MySQL Basic Settings
  • Basic database operation commands

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Users Guide

• Guide
  • Data Structures
• Crate
  • remote control
  • slot
• FIRMWARE
• Qt GUI
• ROOT GUI
  • The main control interface
  • File
    • About
  • Base
    • Base Setup
    • Trigger Filter
    • Energy
    • CFD
    • QDC
    • Decimation
    • Copy Pars
    • Save2File
  • Expert
    • Module Variables
    • CSRA
    • Logic Set
  • Debug
    • Hist & XDT
    • Trace & Baseline
  • Offiline
    • InitData
    • Adjust Par
    • Wave-16
    • Energy-16
    • Orig Energy
    • Calc Energy
    • FF/CFD Thre
    • Energy-FF
    • CFD D/F
    • CFD Frac
    • Energy-CFD
    • QDC
    • FFT
    • Time Diff
    • Simulation
• NOGUI
  • Interface
  • auto run
• Online Stattics
  • ROOT-based graphical interface
  • Web-based graphical interface
• 数据解码
• 事件重构
• Decode
• MakeEvent
• Front Panel
  • Analog Signal Input Connectors(all revisions)
  • LVDS I/O Port (all revisions)
  • Digital I/O Connectors(Rev. F only)
  • Front Panel LEDs (all revisions)
  • 3.3V I/O Connector(Rev. D only)
  • GATE Inputs(Rev. D only)
  • 3.3V I/O Connector(Rev. B and C only)
  • Digital Signals in Standard Firmware(all revisions)
• Logic
  • Logic function
  • Module Fast Trigger(for trigger)
  • Module Validation Trigger(for control logic)
  • Channel Validation Trigger(for trigger/control logic)
  • Veto
  • System FPGA（coincidence/multiplicity）
• Multiple Modules Synchronously
  • Individual Clock Mode
  • PXI Clock Mode
  • Daisy-chained Clock Mode
  • Multi-Crate Clock Mode
    • Installation of Pixie-16 Modules
    • Clock Jumper (JP101) Settings on the Pixie-16 Modules
    • Cable Connections for Pixie-16 Rear I/O Trigger Modules
    • Jumper Settings on the Pixie-16 Rear I/O Trigger Modules
• Update CPLD
  • 6 pin JTAG connector
  • update the CPLD

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Applications

• Applications
• TOF measurement in 100M
  • TAC signal characteristics
  • Experimental results(2017 RIBLL)
• Time Resolution
  • Pulse Generator
  • 100M module
  • 250M module
  • 100M & 250M module
• Recommended Parameters
  • TAC
  • NIM signal
  • HPGe
  • BGO
  • Si
  • LaBr3
• In Beam Gamma
  • Control Interface
  • Veto gate width
  • Peak-to-total

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Programmers Guide

• Developer’s Guide
• PIXIE-16 API
  • XIA API
  • PKU API
• PKU Code
  • Decode
  • GUI
  • MakeEvent
  • OnlineStattics