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User FPGA I/O ports

This section illustrates the I/O ports of the UFPGA. Port names are the same of the VHDL entity top-level ports used in the template and demo firmware.

User’s Code

G port

输入输出控制：

-- 输入
nOEG <= '1';

-- 输出
nOEG <= '0';

NIM/TTL选择控制：

-- NIM
SELG <= '0';

-- TTL
SELG <= '1';