.. UserDPP.rst --- 
.. 
.. Description: 
.. Author: Hongyi Wu(吴鸿毅)
.. Email: wuhongyi@qq.com 
.. Created: 二 10月  1 23:38:02 2024 (+0800)
.. Last-Updated: 日 10月 13 19:47:40 2024 (+0800)
..           By: Hongyi Wu(吴鸿毅)
..     Update #: 2
.. URL: http://wuhongyi.cn 

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UserDPP firmware
##################################################

The firmware developed by Hongyi Wu will soon be updated in this section of the manual.

The firmware of 2730 has an FPGA running clock of 125 MHz. Add up the four sampling points of each clock as one sampling point for processing.



Coming soon...


============================================================
Basic
============================================================

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Input
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.. image:: /_static/img/userdpp_basic_input.png



----------------------------------------------------------------------
UserDPP
----------------------------------------------------------------------


.. image:: /_static/img/userdpp_basic_userdpp.png




============================================================
Logic
============================================================



   
.. 
.. UserDPP.rst ends here